Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Off-chip vias in stacked chips

Off-chip vias in stacked chips

US Patent 9899353 · Granted Feb 20, 2018

Estimated economic value: $11,967,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Expansion controlled structure for direct bonding and method of forming same2025
Integrated cooling assembly with upper and lower channels2025
Embedded organic interposer for high bandwidth2025
Package-on-package assembly with wire bonds to encapsulation surface2025
Package-on-package assembly with wire bonds to encapsulation surface2025
Compressive sensing based image processing2025
Metal pads over TSV2025
Metal pads over TSV2025
3D NAND-high aspect ratio strings and channels2025
Bonded structure including an obstructive element directly bonded to a semicondu2025
Protective elements for bonded structures2025
Circuitry for electrical redundancy in bonded structures2025