{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method and structure to reduce the electric field in semiconductor wiring interconnects", "item": "https://www.patentleaderboard.com/patent/9666529"}]}
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Home › Method and structure to reduce the electric field in semiconductor wiring interconnects

Method and structure to reduce the electric field in semiconductor wiring interconnects

US Patent 9666529 · Granted May 30, 2017

Estimated economic value: $1,983,000 ⓘ

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