Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Undercut insulating regions for silicon-on-insulator device

Undercut insulating regions for silicon-on-insulator device

US Patent 9595578 · Granted Mar 14, 2017

Estimated economic value: $3,628,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Stacked vertical transport field effect transistor with anchors2025
Semiconductor passive device integration for silicon-on-insulator substrate2025
Integratead wet clean for bevel treatments2025
Local interconnects having different material compositions2025
Layered bottom electrode dielectric for embedded MRAM2025
Recessed local interconnect semiconductor memory device2025
Vertically stacked FET with strained channel2025
Read-only memory for chip security that is MOSFET process compatible2025
Nanowire source/drain formation for nanosheet device2025
Strain generation and anchoring in gate-all-around field effect transistors2025
Buried power rail with robust connection to a wrap around contact2025
Semiconductor structure with wrapped-around backside contact2025