Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for dividing testable logic into a two-dimensional grid for physically efficient scan

Method for dividing testable logic into a two-dimensional grid for physically efficient scan

US Patent 9470755 · Granted Oct 18, 2016

Estimated economic value: $7,641,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Physical awareness of test-point sharing in a circuit design2025
Physical awareness of test-point sharing in a circuit design2025
Physical awareness of test-point sharing in a circuit design2025
Systems and methods for reducing test point power consumption in a circuit desig2025
Clock-based test-point flop sharing in a circuit design2025
Clock-based test-point flop sharing in a circuit design2025
Clock-based test-point flop sharing in a circuit design2025
Locking mechanism and core wrapping for IP core2025
IC chip with IC design modification detection2025
IC chip with IC design modification detection2025
IC chip with IC design modification detection2025
Launch off shift process2025