Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › DRAM retention monitoring method for dynamic error correction

DRAM retention monitoring method for dynamic error correction

US Patent 9411678 · Granted Aug 9, 2016

Estimated economic value: $4,794,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High-performance, high-capacity memory modules and systems2025
Memory controller partitioning for hybrid memory system2025
Load-reduced DRAM stack2025
Dynamic, random-access memory with hidden memory scrubbing2025
Semiconductor memory systems with on-die data buffering2025
Semiconductor memory systems with on-die data buffering2025
DRAM interface mode with improved channel integrity and efficiency at high signa2025
Multidrop optical input/output module2025
Dynamic random access memory (DRAM) device with variable burst lengths2025
Memory device having hidden refresh2025
MAC processing pipelines, circuitry to configure same, and methods of operating 2025
MAC processing pipeline having activation circuitry, and methods of operating sa2025