Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs

Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs

US Patent 9252247 · Granted Feb 2, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Wafer-scale direct bonded array core block for an active electronically steerabl2025
Laterally-gated transistors and lateral Schottky diodes with integrated lateral 2025
Self-passivated nitrogen-polar III-nitride transistor2025
Laterally-gated transistors and lateral Schottky diodes with integrated lateral 2024
Low cost panel AESA with thermal management2024
Planar metal Fresnel millimeter-wave lens2024
Ohmic contact for multiple channel FET2023
Dual-band monolithic microwave IC (MMIC) power amplifier2022
Antenna sub-array blocks having heat dissipation2022
Active multi-spectral system for generating camouflage or other radiating patter2021
Wafer structure with mode suppression2021
Highly scaled linear GaN HEMT Structures2020