Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dual-complementary integrating duty cycle detector with dead band noise rejection

Dual-complementary integrating duty cycle detector with dead band noise rejection

US Patent 9246475 · Granted Jan 26, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Linear progression delay register2016
Linear progression delay register2016
Data inversion register technique for integrated circuit memory testing2014
Shielding of datalines with physical placement based on time staggered access2013
Circuit and technique for reducing parity bit-widths for check bit and syndrome 2013
Error correction code (ECC) circuit test mode2012
Circuit and technique for reducing parity bit-widths for check bit and syndrome 2012
Technique for reducing parity bit-widths for check bit and syndrome generation f2011
Using differential data strobes in non-differential mode to enhance data capture2011
Asymetric data path position and delays technique enabling high speed access in 2010
Multi-bank block architecture for integrated circuit memory devices having non-s2010
Data inversion register technique for integrated circuit memory testing2009