{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Path-based floorplan analysis", "item": "https://www.patentleaderboard.com/patent/9189591"}]}
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Home › Path-based floorplan analysis

Path-based floorplan analysis

US Patent 9189591 · Granted Nov 17, 2015

Estimated economic value: $4,921,000 ⓘ

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