Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit models having associated timing exception information therewith for use with electronic design automation

Integrated circuit models having associated timing exception information therewith for use with electronic design automation

US Patent 6678644 · Granted Jan 13, 2004

Estimated economic value: $39,257,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Path-based floorplan analysis2017
Shaping integrated with power network synthesis (PNS) for power grid (PG) alignm2016
Determining a set of timing paths for creating a circuit abstraction2016
Path-based floorplan analysis2015
Semiconductor integrated circuit partitioning and timing2015
Abstract creation2014
Displaying a congestion indicator for a channel in a circuit design layout2014
Optimizing locations of pins for blocks in a hierarchical physical design by usi2006
Method and system for circuit design top level and block optimization2002
Integrated circuit models having associated timing exception information therewi2002
Method and apparatus for irregular datapath placement in a datapath placement to2001
Extracting accurate and efficient timing models of latch-based designs2000