Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints

Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints

US Patent 8977994 · Granted Mar 10, 2015

Estimated economic value: $5,227,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hybrid language model architecture for API orchestration including chain of thou2025
Generative machine learning with retriever having reconfigurable sequence of ran2025
Controlling ingestion of streaming data to serverless function executions2024
Intra-shard parallelization of data stream processing using virtual shards2023
Streaming analytics using a serverless compute system2022
Method, system, and computer program product for implementing prototyping and fl2017
Machine readable products for single pass parallel hierarchical timing closure o2015
Machine readable products for single pass parallel hierarchical timing closure o2015
Multi-phase models for timing closure of integrated circuit designs2015
Multi-phase models for timing closure of integrated circuit designs2015
Methods, systems, and articles of manufacture for implementing full-chip optimiz2015
Methods, systems, and articles of manufacture for synchronous hierarchical imple2015