Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Verification and debugging using heterogeneous simulation models

Verification and debugging using heterogeneous simulation models

US Patent 8868396 · Granted Oct 21, 2014

Estimated economic value: $12,645,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Implementing burst transfers for predicated memory accesses in loop bodies for h2025
Inter-kernel dataflow analysis and deadlock detection2025
Early detection of sequential access violations for high level synthesis2023
Static and automatic inference of inter-basic block burst transfers for high-lev2023
Unified container for hardware and software binaries2023
Hardware-software design flow with high-level synthesis for heterogeneous and pr2023
Data-driven platform characteristics capture and discovery for hardware accelera2022
High-level synthesis implementation of data structures in hardware2022
High-level synthesis vector library for single-instruction multiple data program2022
Hardware-software design flow with high-level synthesis for heterogeneous and pr2021
Method and system providing visualization of sub-circuit iterations based on han2021
Transaction associations in waveform displays2021