Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques

Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques

US Patent 8713501 · Granted Apr 29, 2014

Estimated economic value: $4,552,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method to compute timing yield and yield bottleneck using correlated sample gene2024
Analyzing delay variations and transition time variations for electronic circuit2022
Analyzing delay variations and transition time variations for electronic circuit2020
Circuit timing analysis2020
Analyzing delay variations and transition time variations for electronic circuit2019
Augmented simulation method for waveform propagation in delay calculation2016
Statistical corner evaluation for complex on-chip variation model2014
Efficient data compression for vector-based static timing analysis2014
Simultaneous multi-corner static timing analysis using samples-based static timi2013
Statistical corner evaluation for complex on chip variation model2013
Statistical delay and noise calculation considering cell and interconnect variat2013
Sensitivity-based complex statistical modeling for random on-chip variation2013