Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit having interleaved gridded features, mask set, and method for printing

Integrated circuit having interleaved gridded features, mask set, and method for printing

US Patent 8580685 · Granted Nov 12, 2013

Estimated economic value: $7,244,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuits and processes for protection of standard cell performance fr2021
SRAM cell with T-shaped contact2020
SRAM cell with T-shaped contact2020
SRAM cell with T-shaped contact2019
Integrated circuits and processes for protection of standard cell performance fr2019
SRAM cell with T-shaped contact2018
Method of forming a transistor with an active area layout having both wide and n2018
Methods and devices for determining logical to physical mapping on an integrated2016
Alignment to multiple layers2016
Layout method to minimize context effects and die area2015
Alignment to multiple layers2015
Context protection for a column interleaved memory2015