Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two

Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two

US Patent 9899364 · Granted Feb 20, 2018

Estimated economic value: $23,006,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

SRAM layout for double patterning2024
Integrated circuits and processes for protection of standard cell performance fr2021
SRAM layout for double patterning2020
SRAM cell with T-shaped contact2020
SRAM cell with T-shaped contact2020
Rectangular via for ensuring via yield in the absence of via redundancy2020
SRAM cell with T-shaped contact2019
Integrated circuits and processes for protection of standard cell performance fr2019
SRAM layout for double patterning2019
SRAM cell with T-shaped contact2018
SRAM layout for double patterning2018
Metal on elongated contacts2018