Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Electrically isolated power semiconductor package with optimized layout

Electrically isolated power semiconductor package with optimized layout

US Patent 8455987 · Granted Jun 4, 2013

Estimated economic value: $3,222,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electrical contact for semiconductor package2023
Metal tab for chip assembly2023
Discrete power transistor package having solderless DBC to leadframe attach2022
Lead and lead frame for power package2020
Discrete power transistor package having solderless DBC to leadframe attach2020
Heat transfer plate having small cavities for taking up a thermal transfer mater2019
Power semiconductor device module having mechanical corner press-fit anchors2019
Heat transfer plate having small cavities for taking up a thermal transfer mater2019
Power semiconductor device module having mechanical corner press-fit anchors2018
Direct metal bonding on carbon-covered ceramic contact projections of a ceramic 2018
Inverse diode stack2018
Power semiconductor device module baseplate having peripheral heels2018