Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Accuracy pin-slew mode for gate delay calculation

Accuracy pin-slew mode for gate delay calculation

US Patent 8418108 · Granted Apr 9, 2013

Estimated economic value: $4,611,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Detecting and modeling via during global routing2025
Cell-based pin access location generation2025
Timing-aware and simultaneous optimization of latch clustering and placement in 2025
Tracing and verifying a shared library using blockchain2025
Restructuring algorithm for including user-specified clock instances in a post-C2025
Resistance and capacitance aware preferred layer trimming2025
Skewing level limited clock tree2025
Rule check heatmap prediction2025
Short net pin alignment for routing2025
Logic sharing maximization using non-unique matrix representation2025
Wire density-aware layer assignment2025
Timing-based layer assignment2025