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Home › Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

US Patent 8094503 · Granted Jan 10, 2012

Estimated economic value: $35,136,000 ⓘ

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