Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for mapping design memories to integrated circuit layout

Method and apparatus for mapping design memories to integrated circuit layout

US Patent 8037432 · Granted Oct 11, 2011

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatus for processing signals carrying modulation-encoded parity bits2016
Parallel decoder for multiple wireless standards2016
Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS proce2015
Via-configurable high-performance logic block involving transistor chains2015
Programmable circuit for high speed computation of the interleaver tables for mu2015
Packet router having a hierarchical buffer structure2014
Optimization of data processors with irregular patterns2014
No-delay microsequencer2014
Two-pass linear complexity task scheduler2014
L-value generation in a decoder2014
Data shredding RAID mode2014
Variable parity encoder2014