Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow

Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow

US Patent 7960280 · Granted Jun 14, 2011

Estimated economic value: $4,146,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device with doped region adjacent isolation structure in extension2021
Methods for converting planar designs to FinFET designs in the design and fabric2016
Semiconductor structures and methods for forming isolation between Fin structure2016
Integration scheme for changing crystal orientation in hybrid orientation techno2015
Structure for facilitating the simultaneous silicidation of a polysilicon gate a2015
Method for forming and integrating metal gate transistors having self-aligned co2015
Semiconductor device with stressed fin sections2014
Methods for forming semiconductor structures using selectively-formed sidewall s2014
Integrated circuits having a continuous active area and methods for fabricating 2014
Integrated circuits including multi-gate transistors locally interconnected by c2014
Methods for fabricating FinFET integrated circuits on bulk semiconductor substra2013
Method of forming fully silicided NMOS and PMOS semiconductor devices having ind2013