Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching

Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching

US Patent 7838424 · Granted Nov 23, 2010

Estimated economic value: $4,350,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-buffered register files with shared access circuits2025
Apparatus and method for approximate trilinear interpolation for scene reconstru2025
Apparatus and method for approximate trilinear interpolation for scene reconstru2025
Selective congestion notification by a network interface device2025
Low power flip-flop with reduced parasitic capacitance2023
High performance fast Mux-D scan flip-flop2023
Multibit vectored sequential with scan2022
Low-power single-edge triggered flip-flop, and time borrowing internally stitche2022
High performance fast Mux-D scan flip-flop2022
Double edge triggered Mux-D scan flip-flop2021
Multibit vectored sequential with scan2021
Vectored flip-flop2020