Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Versatile bus interface macro for dynamically reconfigurable designs

Versatile bus interface macro for dynamically reconfigurable designs

US Patent 7619442 · Granted Nov 17, 2009

Estimated economic value: $2,669,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Compiler directed cache coherence for many caches generated from high-level lang2016
Processor and cache arrangement with selective caching between first-level and s2014
Secure cloud computing infrastructure2014
Generation of cache architecture from a high-level language description2013
Generating a module interface for partial reconfiguration design flows2012
Verification of logic core implementation2012
Generating a module interface for partial reconfiguration design flows2011
Methods for automatically generating fault mitigation strategies for electronic 2011
Floating-point processing unit for successive floating-point operations2011
Method and apparatus for providing secure intellectual property cores for a prog2011
Determining sizes of FIFO buffers between functional blocks in an electronic cir2010
Design independent correlation data storage for use with physical design of prog2010