Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

US Patent 7615462 · Granted Nov 10, 2009

Estimated economic value: $23,460,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Stitched sensor for deleting or measuring acting force2024
Semiconductor device package comprising thermal interface layer and method of fa2022
Heating element and method for manufacturing same2019
Three-dimensional stacked substrate arrangements2013
Three-dimensional stacked substrate arrangements2012
Three-dimensional stacked substrate arrangements2011
Cooling micro-channels2010
Cooling micro-channels2010
Integrated re-combiner for electroosmotic pumps using porous frits2010
Integrated re-combiner for electroosmotic pumps using porous frits2010
Method of forming a stack of heat generating integrated circuit chips with inter2010
Method of forming a stack of heat generating integrated circuit chips with inter2010