Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for manufacturing an array of cells including selection bipolar junction transistors

Process for manufacturing an array of cells including selection bipolar junction transistors

US Patent 7563684 · Granted Jul 21, 2009

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Decoding architecture for memory devices2025
Reading a multi-level memory cell2025
Memory devices having one-time-programmable fuses and/or antifuses formed from t2025
Varying-polarity read operations for polarity-written memory cells2025
Unipolar programming of memory cells2025
Vertical memory architecture2025
Devices including a passive material between memory cells and conductive access 2025
Cross-point pillar architecture for memory arrays2025
Decoder architectures for three-dimensional memory devices2025
Folded access line for memory cell access in a memory device2025
Memory device and method for manufacturing the same2025
Techniques for forming self-aligned memory structures2025