Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Channel masking during integrated circuit testing

Channel masking during integrated circuit testing

US Patent 7523370 · Granted Apr 21, 2009

Estimated economic value: $10,385,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for diagnosing failure locations in electronic circuits2018
Method and apparatus for efficient hierarchical chip testing and diagnostics wit2016
Method and system for providing efficient on-product clock generation for domain2014
Method and apparatus for automated extraction of a design for test boundary mode2014
Method and system for reducing switching activity during scan-load operations2013
Fault modeling for state retention logic2012
Low power scan test for integrated circuits2010
System and method for performing logic failure diagnosis using multiple input si2009
Arrangement for testing semiconductor chips while incorporated on a semiconducto2008
Arrangement for testing semiconductor chips while incorporated on a semiconducto2008
Method and system for reducing test data volume in the testing of logic products2006
Method for reducing switching activity during a scan operation with limited impa2006