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Home › Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

US Patent 7485537 · Granted Feb 3, 2009

Estimated economic value: $3,057,000 ⓘ

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