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Home › Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

US Patent 7466591 · Granted Dec 16, 2008

Estimated economic value: $7,709,000 ⓘ

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