Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit and method for reducing power in a memory device during standby modes

Circuit and method for reducing power in a memory device during standby modes

US Patent 7460429 · Granted Dec 2, 2008

Estimated economic value: $734,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for providing symmetrical output data for a double data rat2013
Circuit and method for controlling a clock synchronizing circuit for low power r2013
Circuit and method for controlling a clock synchronizing circuit for low power r2011
Method and apparatus for output data synchronization with system clock in DDR2011
Method and apparatus for providing symmetrical output data for a double data rat2011
Circuit and method for reducing power in a memory device during standby modes2010
Circuit and method for controlling a clock synchronizing circuit for low power r2009
Method and unit for buffer control2009
Method and apparatus for providing symmetrical output data for a double data rat2008
Method and apparatus for decoupling conductive portions of a microelectronic dev2008
Apparatus for measuring parasitic capacitance and inductance of I/O leads on an 2007
Method and apparatus for improving output skew for synchronous integrated circui2007