Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dual chip stack method for electro-static discharge protection of integrated circuits

Dual chip stack method for electro-static discharge protection of integrated circuits

US Patent 7067914 · Granted Jun 27, 2006

Estimated economic value: $5,894,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Structure and method of latchup robustness with placement of through wafer via w2021
Probe for localized neural optogenetics stimulation and neurochemistry recording2020
Method for forming FinFET device structure2020
On-chip DC-DC power converters with fully integrated GaN power switches, silicon2019
Structure and method of latchup robustness with placement of through wafer via w2019
Edge trim processes and resultant structures2018
Wafer handler and methods of manufacture2018
FinFET device structure and method for forming same2018
Integrated DC-DC power converters through face-to-face bonding2018
Structure and method of latchup robustness with placement of through wafer via w2017
3D integrated DC-DC power converters2017
On-chip DC-DC power converters with fully integrated GaN power switches, silicon2017