Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process

Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process

US Patent 6979869 · Granted Dec 27, 2005

Estimated economic value: $4,269,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electrostatic discharge protection circuit having high allowable power-up slew r2015
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submic2012
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submic2011
Circuit protection system2010
Design of silicon-controlled rectifier by considering electrostatic discharge ro2010
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submic2009
Electrostatic discharge series protection2009
RC-triggered ESD power clamp circuit and method for providing ESD protection2008
Bias for electrostatic discharge protection2008
Electrostatic discharge testing2008
Optimization of NMOS drivers using self-ballasting ESD protection technique in f2008
Implantation method to improve ESD robustness of thick gate-oxide grounded-gate 2006