| 9172241 |
Electrostatic discharge protection circuit having high allowable power-up slew rate |
— |
2015-10-27 |
| 8269280 |
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process |
— |
2012-09-18 |
| 7948036 |
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process |
— |
2011-05-24 |
| 7777996 |
Circuit protection system |
William Loh, Ken Doniger, Payman Zarkesh-Ha, Choshu Ito |
2010-08-17 |
| 7763908 |
Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices |
— |
2010-07-27 |
| 7582938 |
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process |
— |
2009-09-01 |
| 7551414 |
Electrostatic discharge series protection |
William Loh, Choshu Ito |
2009-06-23 |
| 7379281 |
Bias for electrostatic discharge protection |
William Loh, Minxuan Liu |
2008-05-27 |
| 7375543 |
Electrostatic discharge testing |
Choshu Ito, William Loh |
2008-05-20 |
| 7317228 |
Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process |
— |
2008-01-08 |
| 7119405 |
Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies |
Yoon Huh, Erhong Li |
2006-10-10 |
| 6979869 |
Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process |
Yoon Huh, Peter Bendix |
2005-12-27 |
| 6347026 |
Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides |
Roberto Sung |
2002-02-12 |
