Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby

Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby

US Patent 6821833 · Granted Nov 23, 2004

Estimated economic value: $4,043,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integration of nanosheets with bottom dielectric isolation and ideal diode2025
Graphene/nanostructure FET with self-aligned contact and gate2024
Heat pipe for vertically stacked field effect transistors2024
Superconducting circuit provided on an encapsulated vacuum cavity2024
Co-integrated logic, electrostatic discharge, and well contact devices on a subs2024
Vacuum encapsulated Josephson junction2023
Qubits with ion implant Josephson junctions2022
System, method and computer program product to extract information from email co2022
Asymmetric high-k dielectric for reducing gate induced drain leakage2021
Asymmetric high-k dielectric for reducing gate induced drain leakage2020
Techniques for creating a local interconnect using a SOI wafer2020
Method of cleaving a single crystal substrate parallel to its active planar surf2020