Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of integrated circuit design by selection of noise tolerant gates

Method of integrated circuit design by selection of noise tolerant gates

US Patent 6490708 · Granted Dec 3, 2002

Estimated economic value: $15,579,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods of manufacturing a gas diffusion layer and an electrochemical cell incor2025
Autonomous driving evaluation using data analysis2025
Double-sided two-way ranging protocol based on composite, ultrasonic tones2023
Infer text classifiers for large text collections2023
Autonomous driving evaluation using data analysis2023
Cascading stack electrochemical fuel cell2023
Microlenses and filter layers for emission control from a curved display2023
Cognitive elevator advertisements2023
Query response using semantically similar database records2023
Polarization mirror HMD with increased brightness2023
Compact high field of view display2023
Dynamic updating of a word embedding model2022