Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for timing abstraction of digital logic circuits

System and method for timing abstraction of digital logic circuits

US Patent 6442739 · Granted Aug 27, 2002

Estimated economic value: $42,233,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Failure prediction of field-deployed mission critical integrated circuit chips u2025
Power estimation using input vectors and deep recurrent neural networks2024
Selecting a subset of training data from a data pool for a power prediction mode2023
System and method for hierarchical power verification2020
System and method for power verification using efficient merging of power state 2019
System and method for reducing power of a circuit using critical signal analysis2016
Verification of complex systems that can be described by a finite state transiti2016
Automated scalable verification for hardware designs at the register transfer le2015
Automated scalable verification for hardware designs at the register transfer le2013
Transistor-level timing analysis using embedded simulation2010
Transistor-level timing analysis using embedded simulation2010
Functional timing analysis for characterization of virtual component blocks2008