Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication

Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication

US Patent 6433427 · Granted Aug 13, 2002

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Intelligent storage device and intelligent storage method2023
Intelligent store system and intelligent store method2023
Method and device for analyzing data2021
Storage device and storage method to identify object using sensing data and iden2021
Omni reflective optics for wide angle emission LED light bulb2014
High reliability high voltage vertical LED arrays2013
Remote control lighting assembly and use thereof2011
Method for self-assembling microstructures2011
Thermal enhanced low profile package structure and method for fabricating the sa2010
Thermal enhanced low profile package structure2009
LED assembly and use thereof2009
Light emitting device2009