Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dummy patterning for semiconductor manufacturing processes

Dummy patterning for semiconductor manufacturing processes

US Patent 6259115 · Granted Jul 10, 2001

Estimated economic value: $4,638,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Composite particulates for use as part of a supporting fill mixture in a semicon2025
Non-volatile memory with silicided bit line contacts2021
Non-volatile memory with silicided bit line contacts2020
Self-aligned trench isolation in integrated circuits2019
Self-aligned trench isolation in integrated circuits2017
Buried hard mask for embedded semiconductor device patterning2017
Non-volatile memory with silicided bit line contacts2017
Self-aligned trench isolation in integrated circuits2016
Integrating transistors with different poly-silicon heights on the same die2016
Buried hard mask for embedded semiconductor device patterning2016
Buried trench isolation in integrated circuits2016
Non-volatile memory with silicided bit line contacts2016