Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure

Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure

US Patent 6153452 · Granted Nov 28, 2000

Estimated economic value: $25,880,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Customized polishing pads for CMP and methods of fabrication and use thereof2019
Integration of shallow trench isolation and through-substrate vias into integrat2017
Remote access of digital identities2016
Form filling with digital identities, and automatic password generation2016
Customized polishing pads for CMP and methods of fabrication and use thereof2016
Scoped resource authorization policies2015
Stacked interconnect heat sink2015
Method of fabrication of through-substrate vias2015
Integrating account selectors with passive authentication protocols2015
Methods for producing in-situ grooves in chemical mechanical planarization (CMP)2015
Methods for producing in-situ grooves in chemical mechanical planarization (CMP)2015
Form filling with digital identities, and automatic password generation2014