Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for protecting gate electrodes of target transistors in the gate array from gate charging by employing free transistors in the gate array

Method and apparatus for protecting gate electrodes of target transistors in the gate array from gate charging by employing free transistors in the gate array

US Patent 6113648 · Granted Sep 5, 2000

Estimated economic value: $299,695,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low leakage state retention synchronizer2016
Latch with a feedback circuit2014
Multiple-domain processing system using hierarchically orthogonal switching fabr2010
Clock synchronizer2010
Logic with state retentive sleep mode2010
Configuration access mechanism for packet switching architecture2008
Deadlock avoidance queuing mechanism2008
Power management over switching fabrics2008
Multiple-domain processing system using hierarchically orthogonal switching fabr2007
Method and apparatus for a switch fabric in a data transport system2007
Ultra-drowsy circuit2007
Scan enabled storage device2006