Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Logic with state retentive sleep mode

Logic with state retentive sleep mode

US Patent 7649385 · Granted Jan 19, 2010

Estimated economic value: $22,167,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatuses, methods, and systems for enhanced matrix multiplier architecture2022
Low leakage state retention synchronizer2016
Latch with a feedback circuit2014
Clock synchronizer2010
Ultra-drowsy circuit2007
Scan enabled storage device2006
Ultra-drowsy circuit2006
Apparatus and circuit having reduced leakage current and method therefor2006
Slave-less edge-triggered flip-flop2005
Apparatus and circuit having reduced leakage current and method therefor2004
Iterative, noise-sensitive method of routing semiconductor nets using a delay no2002
Method and apparatus for protecting gate electrodes of target transistors in the2000