Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit and method for instruction controllable slew rate of bit line driver

Circuit and method for instruction controllable slew rate of bit line driver

US Patent 6005821 · Granted Dec 21, 1999

Estimated economic value: $5,436,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Support for multiple widths of DRAM in double data rate controllers or data buff2021
Double data rate controllers and data buffers with support for multiple data wid2020
Overvoltage protection circuits and methods of operating same2017
Programmable clock drivers that support CRC error checking of configuration data2007
Clock signal generators having programmable full-period clock skew control2006
Multi-FIFO integrated circuit devices that support multi-queue operating modes w2006
Integrated DDR/SDR flow control managers that support multiple queues and MUX, D2006
DRAM interface circuits having enhanced skew, slew rate and impedance control2006
Clock signal generators having programmable full-period clock skew control and m2005
Static timing analysis with simulations on critical path netlists generated by s2003
Clocking scheme for independently reading and writing multiple width words from 2003
Method and apparatus for the automated generation of programmable interconnect m2002