Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Static timing analysis with simulations on critical path netlists generated by static timing analysis tools

Static timing analysis with simulations on critical path netlists generated by static timing analysis tools

US Patent 6553549 · Granted Apr 22, 2003

Estimated economic value: $6,237,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method of full semiconductor chip timing closure2010
Method and system for providing hybrid clock distribution2008
Multi-bit deskewing of bus signals using a training pattern2006
Memory architecture2002
Method and apparatus for the automated generation of programmable interconnect m2002
Method and apparatus for the automated design of memory devices2001
Memory architecture2001
Circuit and method for instruction controllable slew rate of bit line driver1999
Write enabling circuitry for a semiconductor memory1999
Voltage level interface circuit with set-up and hold control1999
Circuit and method for instruction controllable slewrate of bit line driver1998
Output enable access for an output buffer1997