Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for providing optimization parameters to a logic optimizer tool

Method and apparatus for providing optimization parameters to a logic optimizer tool

US Patent 5960184 · Granted Sep 28, 1999

Estimated economic value: $56,412,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for selectively providing hierarchy to a circuit design2004
Spreadsheet driven I/O buffer synthesis process2004
Efficient top-down characterization method2002
Method and apparatus for incremntally optimizing a circuit design2000
Method and apparatus for incremntally optimizing a circuit design2000
Method and apparatus for optimizing a gated clock structure using a standard opt1999
Method and apparatus for optimizing a gated clock structure using a standard opt1999
Method and apparatus for optimizing a circuit design having multi-paths therein1999
Method and apparatus for optimizing a circuit design having multi-paths therein1999
Method and apparatus for monitoring the performance of a circuit optimization to1999
Method and apparatus for monitoring the performance of a circuit optimization to1999
Method and apparatus for identifying gated clocks within a circuit design using 1999