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Home › Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads

Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads

US Patent 5742009 · Granted Apr 21, 1998

Estimated economic value: $4,931,000 ⓘ

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