Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6468834 | Method of fabricating a BGA package using PCB and tape in a die-up configuration | — | 2002-10-22 |
| 6264778 | Reinforced sealing technique for an integrated circuit package | Leonard L. Mora | 2001-07-24 |
| 6069407 | BGA package using PCB and tape in a die-up configuration | — | 2000-05-30 |
| 6047467 | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads | Chin-Ching Huang | 2000-04-11 |
| 5999415 | BGA package using PCB and tape in a die-down configuration | — | 1999-12-07 |
| 5910686 | Cavity down HBGA package structure | Robert J. Martin | 1999-06-08 |
| 5742009 | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads | Chin-Ching Huang | 1998-04-21 |
| 5687474 | Method of assembling and cooling a package structure with accessible chip | Leonard L. Mora | 1997-11-18 |
| 5689091 | Multi-layer substrate structure | Kamran Manteghi | 1997-11-18 |
| 5539151 | Reinforced sealing technique for an integrated-circuit package | Leonard L. Mora | 1996-07-23 |
| 5491362 | Package structure having accessible chip | Leonard L. Mora | 1996-02-13 |
| 5430331 | Plastic encapsulated integrated circuit package having an embedded thermal dissipator | Sang S. Lee | 1995-07-04 |
| 5371321 | Package structure and method for reducing bond wire inductance | Chin-Ching Huang | 1994-12-06 |