Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate

Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate

US Patent 5256582 · Granted Oct 26, 1993

Estimated economic value: $5,113,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low noise JFET2012
Trench isolation comprising process having multiple gate dielectric thicknesses 2011
Reliable high-voltage junction field effect transistor and method of manufacturi2010
Low noise JFET2010
Silicide block isolated junction field effect transistor source, drain and gate2010
Open source/drain junction field effect transistor2009
Versatile system for optimizing current gain in bipolar transistor structures2009
Method to accurately estimate the source and drain resistance of a MOSFET2009
Reliable high-voltage junction field effect transistor and method of manufacture2007
Versatile system for optimizing current gain in bipolar transistor structures2007
Reduce 1/f noise in NPN transistors without degrading the properties of PNP tran2007
Transistors formed with grid or island implantation masks to form reduced diffus2005