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Home › Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology

Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology

US Patent 12144173 · Granted Nov 12, 2024

Estimated economic value: $21,756,000 ⓘ

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