Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Distributed semiconductor die and package architecture

Distributed semiconductor die and package architecture

US Patent 11894359 · Granted Feb 6, 2024

Estimated economic value: $35,892,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit interconnect structures with a metal chalcogenide liner2025
Package architecture of photonic system with vertically stacked dies having plan2025
Package architecture of photonic system with vertically stacked dies having plan2025
Package architecture of scalable compute wall having compute bricks with vertica2025
Package architecture of scalable compute wall having compute bricks with vertica2025
Performing distributed processing using distributed memory2025
BGA stiffener attachment with low Eolife adhesive strength at high solder joint 2025
Embedded dynamic random-access memory (eDRAM) to operate based on data access ch2025
Ultra-thin, hyper-density semiconductor packages2025
Multi-chip packaging2025
Integrated planar transistors and memory cell array architectures2025
Moisture seal coating of hybrid bonded stacked die package assembly2025