Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column

US Patent 11581037 · Granted Feb 14, 2023

Estimated economic value: $12,121,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic random-access memory (DRAM) on hot compute logic for last-level-cache2025
Intelligent encoding method and system, and electronic device2025
Partial sum management and reconfigurable systolic flow architectures for in-mem2025
Partial sum management and reconfigurable systolic flow architectures for in-mem2025
Method and terminal for identifying barcode2024
Trench power rail in cell circuits to reduce resistance and related power distri2024
Trench power rail in cell circuits to reduce resistance and related power distri2024
Digital compute in memory2024
Digital compute in memory2024
Systems and methods for modifying neural networks for binary processing applicat2023
Compute-in-memory bitcell with capacitively-coupled write operation2023
Compute-in-memory bitcell with capacitively-coupled write operation2023