{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Device, method and system to provide a stressed channel of a transistor", "item": "https://www.patentleaderboard.com/patent/11557676"}]}
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Home › Device, method and system to provide a stressed channel of a transistor

Device, method and system to provide a stressed channel of a transistor

US Patent 11557676 · Granted Jan 17, 2023

Estimated economic value: $13,997,000 ⓘ

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