Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of making multiple nano layer transistors to enhance a multiple stack CFET performance

Method of making multiple nano layer transistors to enhance a multiple stack CFET performance

US Patent 11552080 · Granted Jan 10, 2023

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

3D isolation of a segmentated 3D nanosheet channel region2025
3D isolation of a segmentated 3D nanosheet channel region2025
3D advanced transistor architecture integrated with source/drain spider design2025
3D hybrid memory using horizontally oriented conductive dielectric channel regio2025
High performance 3D compact transistor architecture2025
3D horizontal DRAM with in-situ bridge2025
Three-dimensional plurality of N horizontal memory cells with enhanced high perf2025
In-situ lithography pattern enhancement with localized stress treatment tuning u2025
Vertical transistors and methods for forming the same2025
Compact 3D design and connections with optimum 3D transistor stacking2025
3D horizontal memory cell with sequential 3D vertical stacking2025
3D horizontal memory cell with sequential 3D vertical stacking2025