Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High performance circuit applications using stacked 3D metal lines

High performance circuit applications using stacked 3D metal lines

US Patent 11171208 · Granted Nov 9, 2021

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatus and method for wafer alignment2025
3D isolation of a segmentated 3D nanosheet channel region2025
Method for chuck compensation via wafer shape control2025
Wafer chuck designs and methods for retaining a processing liquid on a surface o2025
3D isolation of a segmentated 3D nanosheet channel region2025
3D advanced transistor architecture integrated with source/drain spider design2025
Wet-dry bilayer resist2025
3D hybrid memory using horizontally oriented conductive dielectric channel regio2025
High performance 3D compact transistor architecture2025
Method to form narrow slot contacts2025
3D horizontal DRAM with in-situ bridge2025
Three-dimensional plurality of N horizontal memory cells with enhanced high perf2025